The present invention relates to memory multiplex address systems.
Typically, computer processors have a certain maximum number of bits with which to specify an address. This set of addresses define an address space in which peripherals to the processor must be placed. Thus, in the prior art, read only memories (ROM's), random access memories (RAM's) and the CRT refresh memory associated with a processor include address spaces respectively allocated within the address space of the processor. FIG. 1 shows a typical example of a memory map obtained by a typical allocation of processor address spaces. As illustrated in the drawing, 16K bytes from address 0000 HEX are allocated to ROM 100, 16K bytes from address 4000 HEX to ROM 102, 16K bytes from address 8000 HEX to RAM 104, 8K bytes from address C000 HEX to RAM 106, and addresses from E000 HEX to FFFF HEX to CRT refresh memory 108. In total, the address space includes 64K bytes, the maximum number of bytes addressable with 16 bits of information.
Recently, the length and complexity of software have markedly increased, so an address space of nearly 64K bytes is required simply for operation of the program. Thus, ROM's 100 and 102 and RAM's 104 and 106 must be expanded to cover the entire 64K byte memory space.
The number of pixels included in a CRT display has also had a tendency to increase as resolution has increased. To store this increased number of pixels, an address space of nearly 16K bytes is needed for CRT refresh memory 108. This is the minimum memory capacity that will be necessary for future graphic displays.
However, the address space included in a processor is physically limited by the number of address bits that can be handled. A conventional processor can handle 16 address bits which can individually address no more than 64K bytes of memory. This results in severe restrictions in system design.